Microelectronics Development Division Projects
Following are some of the ongoing projects currently progressing under Microelectronics Development Division.
VLSI & Embedded processor Design
Digital Programmable Hearing Aid
A project for development -Fabrication of ASIC (Application Specific Integrated Circuit) productionization of Digital Programmable Hearing Aid and its deployment is being implemented by CDAC, Thiruvananthapuram with an outlay of Rs. 2547.60 lakh.
An ASIC -NAADA based Digital Programmable Hearing Aid- TARANG has been designed & fabricated using130 nano-meter technology and is successfully tested for its functionality for the hearing impaired patients. Both Body worn and behind-the-ear type DPHAs have been developed using this ASIC. The Body Worn (BW) type DHPA is designed and tested and its environmental testing is completed as per IS:10775-1984. The DPHA module- TARANG has many technologically advanced features, and is customizable and reprogrammable, to address the needs of the hearing-impaired millions in our country in a standardized hardware product. In a true vertically integrated approach, the basic electronics ASIC NAADA, the TARANG product and the SHRUTHI customization software is designed, to suit a wide range of hearing profiles - mild, moderate, severe and profound hearing losses. Completing two years of field trials all over the country through leading national institutions such as All India Institute of Medical Science, Delhi, All India Institute of Speech & hearing, Mysore, Ali Yavar Jung National Institute for the Hearing Handicapped, Mumbai, Christian Medical College (CMC) Vellore, etc., the product has successfully obtained BIS certification by meeting and exceeding the relevant standards. One patent application is filed for the technology developed under the project. TARANG is designed in both Body Worn and Behind The Ear form factors, involving precision components, tools and dies; and is engineered for high-volume manufacture at low cost. TARANG is expected to bring in a paradigm change in addressing hearing disability at a cost much lower than equivalent products presently available in the market. 3000 units of TARANG have been supplied to ALIMCO, Ministry of Social Justice & Empowerment, Govt. of India. TARANG received the President's Award in 2013, for Best Indian Product to address the needs of the Physically Challenged. Transfer of Technology is in progress for indigenous manufacture.
Low Power CODEC for Digitally Programmable Hearing Aids
A Low Power CODEC for Digitally Programmable Hearing Aids is being designed and developed by IIT Madras under a project with an outlay of Rs. 125.49 Lakh, which would be used as a front end for Digital Programmable Hearing Aids. The complete integrated IC with all the blocks included have been designed, fabricated and packaged in a QFN32 package with the required pin configuration. This IC will replace the imported IC being used in the Digital Programmable Hearing Aid being developed by CDAC
ViSMA – Virtualization and Security aware Multi-core Architecture
The Project has been initiated at IISc Bangalore with an Outlay Rs. 55.95 Lakhs .The aim of the project is to carry out a research investigation for specifying the architecture of a Virtualization and Security aware Multi-core Processor. Such a processor architecture bears the combined advantage of achieving hardware consolidation and security, will overcome the large software overheads experienced in traditional virtualization solutions, and also close the security holes observed in current day multi-core systems. The ViSMA high level architecture will be modelled as a set of computing, communicating and storage resources. The micro-architecture will have mechanisms to expose these resources at the level of user applications and allow application level management of resources. T
Micro Electro Mechanical Systems (MEMS)
MEMS based sensors
Development of Micro Electro Mechanical Systems (MEMS) based Integrated Micro Gas Sensor for sensing Volatile Organic Compounds (VOC) and Pollutant Gases like Benzene, Ethanol, Methane, Methanol and Propanol & Pollutant gases viz. Ammonia, Carbon dioxide, Carbon monoxide, Hydrogen sulphide, Nitrogen compounds and Sulphur dioxide in the air is being implemented by CEERI Pilani with an outlay of Rs. 348.70 lakh. 2 different sensing layers viz. Zinc Oxide and Titanium oxide (TiO2) have been developed. Design of a micro heater is completed. The temperature creation and response characteristics for identified VOCs and polluting gases has been carried out. The temperature creation and response characteristics has been completed for most of the gases. Handheld devices for ammonia and carbon monoxide gas sensors are being developed. The sputter deposition equipment has been procured and installed. Three patents are being filed under the project.
Facilities for fabrication of MEMS devices
The Project has been initiated with an outlay Rs.326.436 Lakhs for setting up MEMS fabrication facilities at Tezpur University. Facilities for fabrication of MEMS are being set up to impart training to Ph. D. scholars, PG students from in-house i.e. the Tezpur University and researchers from nearby institutes and research organizations for fabrication of MEMS devices.
Low temperature and low pressure Cu-Cu fine pitch bonding for vertical (3-D) integration
The Project has been initiated at IIT Hyderabad to develop future solutions for vertical integration of MEMS and CMOS with an outlay of Rs. 279.832 Lakhs. The goal of this research project is to identify and develop solutions for future integration of MEMS and CMOS, CMOS to CMOS etc. to enable performance enhancement and miniaturization. The specific objectives of the project are (a) Achieving three-dimensional (3D) integration technology that enable high inter-block electrical connection and hermetic sealing by metallic bonding, (b) Demonstration of outsourced MEMS sensor vertically stacked with wafer using platform developed under the project and (c) use MEMS device (Antenna on Si) for testing the interconnect technology developed under the project.
Analog and Mixed Signal Circuit Design
(i) Centre for Analog Mixed Signal Integrated Circuit Design
The project is being implemented by IIT Madras with an outlay of Rs. 303.27 lakhs. The focus of project is on setting up centre for design, Testing and Characterization of Ultra-High Speed data Communication and Data Conversion Analog Mixed Signal Integrated Circuit. The institute has also specialised in development of low power analog and mixed signal designs. Some of the designs carried out are:
- Continuous-time Delta Sigma (DS) analog to digital converter incorporating the fast loop resulting in the highest sampling rate and the highest signal bandwidth reported thus far in a 180nm CMOS process
- A 1Giga Sample per second DS ADC incorporating the assisted opamp technique
- An 18 bit audio DS modulator fabricated in 180nm CMOS was designed, fabricated, and tested. The DAC architecture in the audio DS modulator meets the stringent noise requirements at the high resolution.
- memoryless DS modulator without internal reset.
- duobinary test interface for high speed data transfer
- 17 bit audio continuous time delta-sigma ADC
- decimation filter
4 (2 International + two Indian) patents have been filed under the project.
(ii) Design of Mixed Signal Circuits for Instrumentation Applications at CEERI, Pilani
Project being implemented by CEERI, Pilani with an outlay of Rs. 231.72 lakh, focuses on design of Analog and Mixed ICs for Instrumentation Applications. 10 Bits Successive Approximation (SAR) ADC and 10 bit DAC has been designed, fabricated, tested and characterised for use in pressure sensor electronic circuitry. Capabilitiesare developed for designing circuits for conditioning and processing the sensor output. Attempts are being made to design and fabricate MEMS and CMOS circuitry in a single chip. Synthesis tool has been developed for schematic/layout level synthesis alongwith the frontend GUI. The netlist optimized for power consumption and corresponding layout are obtained from schematic synthesis for a range of specifications for Opamp and comparator blocks.
(iii) Analog Mixed Signal and RF IC development and Test for Biomedical Applications.
The project being implemented by IIT Bombay with an outlay of Rs. 193.79 lakh aims at development of expertise in the design and testing of analog, mixed signal & RF ICs for bio-medical applications. 3 ICs dedicated for bio-medical applications would be designed, fabricated and tested under the project viz.
- General-purpose Low-power analog signal conditioning chip for portable and personal health-care monitoring applications.
- Low-power analog ECG signal conditioning chip with on-chip wireless connectivity for remote health care.
- Low-power pulse oximetry, bio-sensor analog signal conditioning and modulation and bio telemetry test chip.
IIT Bombay has completed design and fabrication of a reference generators and drivers, ECG instrumentation amplifier and Operational amplifiers.
(iv) Design and Implementation of Low Power Analog front end Modules for wireless Sensor Networks
The project being implemented by NIT, Tiruchirappalli with an outlay of Rs. 39.00 lakhs aims to study the analog modules proposed for design of a Low Power Analog front end Modules for wireless Sensor Networks, identify the blocks which can be optimised for minimizing the power dissipation, design and implementation of LNA, Power amplifier, mixer, frequency synthesizers, programmable filters, modulator, demodulator and analog to digital converters targeted for WSN in 0.18 micron technology, fabrication and testing of the transceiver. Design of an LNA, Power amplifier, mixer, frequency synthesizers and programmable filters is completed. The fabrication of these designs is yet to be taken up.
(v) Design and Characterization of CMOS based Millimeter-wave Components for 60-GHz Integrated Broadband Transceivers
The Project has been initiated at IISc Bangalore with an Outlay Rs. 488.11 Lakhs. The objective of this project is to design and characterize CMOS based integrated circuit components for 60-GHz broadband communication applications. This would involve:
- The design of key 60-GHz receiver and transmitter building blocks using a commonly available CMOS technology and industry-standard CAD tools.
- The architectural specification of the receiver and transmitter and evaluation of techniques that increase the efficiency of spectrum usage at 60-GHz.
- Characterization of the circuits designed at 60-GHz using a proposed state-of-the-art circuit characterization facility.
A low noise amplifier will be developed, operational up to 20 GHz, for industry application.
Modeling & simulation CAD tool
Thermal aware testing of VLSI circuits and systems
Strategies are to be developed for ensuring low temperature during VLSI circuit testing and thermal aware scheduling for testing System-on-Chip (SoC) and Network-on-Chip (NoC) designs under the project being implemented by IIT Kharagpur with an outlay of Rs. 49.91 lakhs. Thermal aware reordering of test vectors for Thermal aware Automated Test Pattern Generator (ATPG) design, don' t care filling and Network-on-Chip testing is completed. Memory testing, Thermal aware SoC testing, Pseudorandom testing and Thermal aware DFT architecture design are under progress.